Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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Document Table of Contents

29.1.2. HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges

Table 236.  HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges and Clocks

Interface Name

Description

Associated Clock Interface

h2f_axi_master 

HPS-to-FPGA AXI master interface

h2f_axi_clock

h2f_lw_axi_master 

HPS-to-FPGA lightweight AXI master interface

h2f_lw_axi_clock

The HPS-to-FPGA interface is a configurable data width AXI master (32-, 64-, or 128-bit) that allows HPS masters to issue transactions to the FPGA fabric.

The lightweight HPS-to-FPGA interface is a 32-bit AXI master that allows HPS masters to issue transactions to the FPGA fabric.

Other interface standards in the FPGA fabric, such as connecting to Avalon-MM interfaces, can be supported through the use of soft logic adapters. The Platform Designer (Standard) system integration tool automatically generates adaptor logic to connect AXI to Avalon-MM interfaces.

Each AXI bridge accepts a clock input from the FPGA fabric and performs clock domain crossing internally. The exposed AXI interface operates on the same clock domain as the clock supplied by the FPGA fabric.

Latency Support for (32-,64, or 128-bit)