Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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Document Table of Contents

11.4.11. Debug Clocks

Table 102.   CoreSight* Clocks

Port Name

Clock Source

Signal Name

Description

ATCLK

Clock manager

cs_at_clk

Trace bus clock.

CTICLK (for CTI)

Clock manager

cs_at_clk

Cross trigger interface clock for CTI. It can be synchronous or asynchronous to CTMCLK.

CTICLK (for FPGA‑CTI)

FPGA fabric

cs_at_clk

Cross trigger interface clock for FPGA‑CTI.

CTICLK (for CTI-0 and CTI-1)

Clock manager

mpu_clk

Cross trigger interface clock for CTI‑0 and CTI‑1. It can be synchronous or asynchronous to CTMCLK.

CTMCLK (for csCTM)

Clock manager

cs_pdbg_clk

Cross trigger matrix clock for csCTM. It can be synchronous or asynchronous to CTICLK.

CTMCLK (for CTM)

Clock manager

mpu_clk

Cross trigger matrix clock for CTM. It can be synchronous or asynchronous to CTICLK.

DAPCLK

Clock manager

cs_pdbg_clk

DAP internal clock. It must be equivalent to PCLKDBG.

PCLKDBG

Clock manager

cs_pdbg_clk

Debug APB* (DAPB) clock.

HCLK

Clock manager

cs_pdbg_clk

Used by the AHB* -Lite master inside the DAP. It is asynchronous to DAPCLK. In the HPS, the AHB* -Lite port uses same clock as DAPCLK.

PCLKSYS

Clock manager

cs_pdbg_clk

Used by the APB* slave port inside the DAP. It is asynchronous to DAPCLK.

SWCLKTCK

JTAG interface

dap_tck

The SWJ-DP clock driven by the external debugger through the JTAG interface. It is asynchronous to DAPCLK. When through the JTAG interface, this clock is the same as TCK of the JTAG interface.

TRACECLKIN

Clock manager

cs_trace_clk

TPIU trace clock input. It is asynchronous to ATCLK. In the HPS, this clock can come from the clock manager or the FPGA fabric.