Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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12.4.8. ECC Controller Clocks

The ECC controller for each ECC-protected memory operates at the same clock frequency as its associated RAM port.

The ECC register interface, however, is in the l4_mp_clk domain. The clock source names for each ECC controller and its RAM are determined by the specific peripheral.

Table 117.   Clock Source for Each ECC Controller and Memory

ECC Memory

Functional Clock

On-chip RAM

l3_main_free_clk

USB

asynchronous l4_mp_clk

SD/MMC

Port A read and write: cclk_in
Port B read and write: l4_mp_clk

Ethernet MAC (Rx FIFO)

Read: ap_clk
Write: clk_rx_int

Ethernet MAC (Tx FIFO)

Read: ap_clk
Write: clk_tx_int

DMA

l4_main_clk

NAND (ECC Buffer)

nand_clk

NAND (Write FIFO)

Write: nand_x_clk
Read: nand_clk

NAND (Read FIFO)

Read: nand_x_clk
Write: nand_clk

QSPI

l4_mp_clk