Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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11.4.10.5. TPIU

Figure 49. Trace Clock and Trace Data Width
Table 101.   TPIU SignalsThe following table lists the signal descriptions between the TPIU and FPGA.
Signal Description
h2f_tpiu_clk_ctl Selects whether trace data is captured using the internal TPIU clock, which is the dbg_trace_clk signal from the clock manager; or an external clock provided as an input to the TPIU from the FPGA.

0 - use h2f_tpiu_clock_in

1 - use internal clock

Note: When the FPGA is powered down or not configured the TPIU uses the internal clock.
h2f_tpiu_data[16] 16-bit trace data bus. Trace data changes on both edges of h2f_tpiu_clock.
h2f_tpiu_clock_in Clock from the FPGA used to capture trace data.
h2f_tpiu_clock Clock output from TPIU