Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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Document Table of Contents

A.4.4.1.2. CSEL Settings for the SD/MMC Controller

Table 315.  SD/MMC Controller Clock Options Based on CSEL and HPS_CLK fuse settings
Note: The osc1_clk signal is sourced from the external oscillator input, HPS_CLK1.

CSEL [3:0] Fuse Values

HPS CLK Fuse Value

Required Input Clock Range

Controller Clock Controller Clock Frequency ID Mode: Baud Rate Divisor ID Mode: Device Clock Data Transfer Mode: Baud Rate Divisor Data Transfer Mode: Device Clock PLL Status

0x0-0x1 and 0x3-0xF

1 60-200 MHz (Secure Bypass) cb_intosc_hs_clk/4 15-50 MHz 128 29-97.75 KHz 4 937.5 KHz-3.125 MHz

Bypass

0x2 1 30-100 MHz (Secure PLL) cb_intosc_ls_clk/8 2.75-12.5 MHz 32 29-97.75 KHz

1 (Bypass)

687.5 KHz-3.125 MHz Locked
0x1 0 10-50 MHz (Untouched PLL) osc1_clk/4 2.5-12.5 MHz 32 19.5-97.75 KHz

1 (Bypass)

625 KHz-3.125 MHz

Untouched

0x0 and 0x2-0x6 0 10-50 MHz (PLL Bypass) osc1_clk/4 2.5-12.5 MHz 32 19.5-97.75 KHz

1 (Bypass)

625 KHz-3.125 MHz

Bypass

0x7

0 10-15 MHz osc1_clk*0.8333 8.333-12.5 MHz 32 65-97.75 KHz

1 (Bypass)

2.08-3.125 MHz Locked

0x8

0 15-20 MHz osc1_clk*0.625 9.375-12.5 MHz 32 73-97.75 KHz

1 (Bypass)

2.34-3.125 MHz Locked
0x9 0 20-25 MHz osc1_clk/2 10-12.5 MHz 32 78.13-97.75 KHz

1 (Bypass)

2.5-3.125 MHz Locked
0xA 0 25-30 MHz osc1_clk*0.4166 10.4175-12.5 MHz 32 81.25-97.75 KHz

1 (Bypass)

2.60-3.125 MHz Locked
0xB 0 30-35 MHz osc1_clk*0.3571 10.715-12.5 MHz 32 83.5-97.75 KHz

1 (Bypass)

2.68-3.125 MHz Locked
0xC 0 35-40 MHz osc1_clk*0.3125 10.9375-12.5 MHz 32 85.25-97.75 KHz

1 (Bypass)

2.75-3.125 MHz Locked
0xD 0 40-45 MHz osc1_clk*0.2777 11.111-12.5 MHz 32 86.75-97.75 KHz

1 (Bypass)

2.78-3.125 MHz Locked
0xE 0 45-50 MHz osc1_clk/4 11.25-12.5 MHz 32 87.75-97.75 KHz

1 (Bypass)

2.81-3.125 MHz Locked