Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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28.2.2. FPGA-to-HPS SDRAM Interface

In the FPGA-to-HPS SDRAM interface table, use the F2SDRAM port configuration pull-down menu to choose bus widths for each SDRAM. You can add one to three SDRAM ports that make the HPS SDRAM subsystem accessible to the FPGA fabric.

The following table shows the width options for the SDRAM ports in Platform Designer (Standard).

Table 228.  FPGA-to-HPS SDRAM Port and Interface Names
Port configuration F2SDRAM 0 F2SDRAM 1 F2SDRAM 2
1 AXI-32 AXI-32 AXI-32
2 AXI-64 AXI-64 AXI-64
3 AXI-128 unused AXI-128
4 AXI-128 AXI-32 AXI-64
Table 229.  FPGA-to-HPS SDRAM Port and Interface Names

Port Name

Interface Name

F2SDRAM 0

f2sdram0_data

f2sdram0_clock

F2SDRAM 1

f2sdram1_data

f2sdram1_clock

F2SDRAM 2

f2sdram2_data

f2sdram2_clock

Note: You can configure the slave interface to a data width of 32-, 64-, 128-bits. To facilitate accessing this slave from a memory-mapped master with a smaller address width, you can use the Intel® Address Span Extender.
Warning: To avoid memory aliasing issues, ensure that Avalon-MM burst transactions into the HPS do not cross the 4 KB address boundary restriction specified by the AXI protocol.