Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

A.8.2. Arria 10 SoC FPGA Partial Reconfiguration Sequence Through FPGA Manager

Partial reconfiguration allows you to reconfigure part of the device while other sections remain running. This implementation divides the design in to a static region and a partial reconfiguration region.

  • Static Region: Comprised of hard memory controller I/O, shared I/O, FPGA I/O and a portion of your FPGA design
  • Dynamic Region: Remaining portion of FPGA design

The HPS performs partial reconfiguration while the FPGA portion of the device is in user mode. The following sequence suggests one way for software to perform a partial configuration. When using this sequence:

  • If f2s_pr_ready=1 and f2s_pr_error=0 in the imgcfg_stat register of the FPGA Manager, begin at step 9.
  • If the f2s_pr_ready bit in the imgcfg_stat register of the FPGA Manager is clear, then begin the sequence at step 1.

If an HPS warm reset occurs in the middle of a partial reconfiguration, software must repeat the steps for partial configuration. After an HPS cold reset, software must repeat the steps for Arria 10 SoC FPGA Configuration Sequence Through FPGA Manager.

  1. Read the f2s_usermode bit of the imgcfg_stat register in FPGA Manager to ensure that the FPGA is in user mode.
  2. Read the f2s_msel[2:0] field in the imgcfg_stat register to verify that the configuration mode is the passive fast (000) or passive slow (001). The FPGA manager only supports passive parallel programming.
  3. Set the cdratio bit of the imgcfg_ctrl_02 register to match the characteristics of the partial reconfiguration image and configure the cfgwidth bit of the imgcfg_ctrl_02 register to 0. Partial reconfiguration only supports 16-bit passive parallel programming.
  4. Prepare for partial reconfiguration. Set the en_cfg_ctrl bit of the imgcfg_ctrl_02 register to give the FPGA manager control of the configuration input signals.
    1. Read and confirm that s2f_pr_request=0 in the imgcfg_ctrl_01 register and s2f_nconfig=1 in the imgcfg_ctrl_00 register.
    2. Drive the chip select signal by clearing the s2f_nce bit in the imgcfg_ctrl_01 register.
    3. Enable overrides for configuration data and control by setting the en_cfg_ctrl bit in the imgcfg_ctrl_02 to 1.
    4. Disable overrides that are not used for partial reconfiguration by programming the following bits in the imgcfg_ctrl_00 register:
      • s2f_condone_oe = 0
      • s2f_nstatus_oe = 0
      • s2_nconfig = 1
      • s2f_nenable_condone = 1
      • s2f_nenable_nstatus = 1
      • s2f_nenable_nconfig = 0
  5. Enable HPS to override the DATA, DCLK, nCE and PR_REQUEST signals to the CSS by clearing the s2f_nenable_config bit in the imgcfg_ctrl_01 register.
  6. Run DCLK to clear any errors. Write a value of 0x100 to the dclkcnt register to generate 256 DCLK cycles. Poll the dclkstat register until dcntdone=1. You must implement a timeout in your software loop that either exits with an error or restarts at step 1 if dcntdone is not set after a period of time.
  7. Initiate a partial reconfiguration request.
    1. Set the s2f_pr_request bit of the imgcfg_ctrl_01 register to assert PR_REQUEST
    2. Write 0x7FF to the dclkcnt register.
    3. Poll the dclkstat register until dcntdone=1 .Again, you must implement a timeout in your software loop that either exits with an error or restarts at step 1 if dcntdone is not set after a period of time.
  8. Poll the f2s_pr_ready bit and the f2s_pr_error bit in the imgcfg_stat register. When f2s_pr_ready=1, the PR_READY signal is asserted. Alternately, the FPGA Manager can be configured to generate an interrupt when the PR_READY signal is asserted. If f2s_pr_error=1, you cannot continue with partial reconfiguration because security is preventing the software from updating the configuration. Intel recommends that your software routine implement an exit with a timeout error when f2s_pr_ready and f2s_pr_error continue to read as 0 after ten register reads.
  9. When the PR_READY signal is asserted, write the partial reconfiguration image to the img_data_w register in the FPGA Manager. You can also choose to use a DMA to transfer the configuration image from a peripheral device to the FPGA manager.
  10. Poll the imgcfg_stat register to observe the f2s_pr_done and f2s_pr_error bits. When the f2s_pr_done bit is set, partial FPGA reconfiguration is complete. If f2s_pr_done or f2s_pr_error is not set to 1 after reading the imgcfg_stat register ten times, generate a timeout error and continue on to the next step.
  11. Clear the s2f_pr_request bit of the imgcfg_ctrl_01 register to deassert PR_REQUEST.
  12. Poll the dcntdone bit of the dclkstat register until it reads as 1, which indicates that all the DCLKs have been sent.
  13. Write a 1 to the dcntdone bit of the dclkstat register to clear the completed status flag.
  14. Disable the DATA path and DCLK by clearing the en_cfg_ctrl bit of the imgcfg_ctrl_02 register.
  15. Disable the chip select. Set the s2f_nce bit in the imgcfg_ctrl_01 register.
  16. Disable overrides to the nCONFIG, DATA and DCLK signals by setting the s2f_nenable_config in the imgcfg_ctrl_01 register.
  17. Check that user mode is enabled and the configuration is done by checking that the bits below have the following values:
    • f2s_usermode=1 in the imgcfg_stat register
    • f2s_nstatus_pin=1 in the imgcfg_stat register
    • f2s_condone_pin=1 in the imgcfg_stat register