Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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4.1.3.1. Modules Requiring Software Deassert

The reset manager leaves the reset signal asserted on certain modules even after the rest of the HPS has come out of reset. These modules are likely to require software configuration before they can safely be taken out of reset.

When a module that has been held in reset is ready to start running, software can deassert the reset signal by writing to the appropriate register, shown in the following table.

Table 27.  Module Reset Signals and Registers
HPS Peripheral Reset Register Module Reset Signal Reset Group
MPU mpumodrst mpu_cpu_rst_n[1] MPU
Watchdog per1modrst watchdog_rst_n[1:0] PER1
Timer per1modrst l4sys_timer_rst_n[1:0] PER1
Timer per1modrst sp_timer_rst_n[1:0] PER1
I2C per1modrst i2c_rst_n[4:0] PER1
UART per1modrst uart_rst_n[1:0] PER1
GPIO per1modrst gpio_rst_n[2:0] PER1
DMA per1modrst dma_periph_if_rst_n[7:0] PER1
Ethernet MAC per0modrst emac_rst_n[2:0] PER0
USB 2.0 OTG per0modrst usb_rst_n[1:0] PER0
NAND per0modrst nand_flash_rst_n PER0
Quad SPI per0modrst qspi_flash_rst_n PER0
SPI Master per0modrst spim_rst_n[1:0] PER0
SPI Slave per0modrst spis_rst_n[1:0] PER0
SD/MMC per0modrst sdmmc_rst_n PER0
DMA per0modrst dma_rst_n PER0
HPS-to-FPGA Bridge brgmodrst hps2fpga_bridge_rst_n Bridge
FPGA-to-HPS Bridge brgmodrst fpga2hps_bridge_rst_n Bridge
Lightweight HPS-to-FPGA Bridge brgmodrst lwhps2fpga_bridge_rst_n Bridge
FPGA-to-SDRAM port 0 brgmodrst f2s_sdram_bridge0_rst_n Bridge
FPGA-to-SDRAM port 1 brgmodrst f2s_sdram_bridge1_rst_n Bridge
FPGA-to-SDRAM port 2 brgmodrst f2s_sdram_bridge2_rst_n Bridge
SDRAM Scheduler brgmodrst ddr_scheduler_rst_n Bridge