Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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29.5.1.1. NAND Flash Controller Interface

Table 239.  NAND Flash Controller Interface Platform Designer (Standard) Port Mappings
Platform Designer (Standard) Port Name Routed to FPGA Routed to HPS I/O HPS Pin Name
nand_adq_i[15:0] Yes Yes NAND_ADQ[15:0]
nand_adq_oe Yes Yes
nand_adq_o[15:0] Yes Yes
nand_ale_o Yes Yes NAND_ALE
nand_ce_o[3:0] Yes, 4 chip enables Yes, 1 chip enable NAND_CE_N
nand_cle_o Yes Yes NAND_CLE
nand_re_o Yes Yes NAND_RE_N
nand_rdy_busy_i[3:0] Yes, 4 ready/busy signals Yes, 1 ready/busy signal NAND_RB
nand_we_o Yes Yes NAND_WE_N
nand_wp_o Yes Yes NAND_WP_N