Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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30. Simulating the HPS Component

This section describes the simulation support for the hard processor system (HPS) component. The HPS simulation models provide bus functional models of the HPS and FPGA fabric and a simulation model of the interface to SDRAM memory.

The HPS simulation support does not include modules implemented in the HPS, such as the Arm* Cortex* ‑A9 MPCore* processor.

The simulation support files are specified when the HPS component is instantiated in the Platform Designer (Standard) system integration tool. When you enable a particular HPS-FPGA interface, Platform Designer (Standard) provides the corresponding model during the generation process.

The HPS simulation support enables you to develop and verify your own FPGA user logic or intellectual property (IP) that interfaces to the HPS component.

The simulation model supports the following interfaces:

  • Clock and reset interfaces
  • FPGA-to-HPS Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced eXtensible Interface ( AXI* ) slave interface
  • HPS-to-FPGA AXI master interface
  • Lightweight HPS-to-FPGA AXI master interface
  • Microprocessor unit (MPU) general‑purpose I/O (GPIO) interface
  • MPU standby and event interface
  • Interrupts interface
  • Direct memory access (DMA) controller peripheral request interface
  • Debug Advanced Peripheral Bus ( APB* ) interface
  • System Trace Macrocell (STM) hardware event
  • FPGA cross trigger interface (CTI)
  • FPGA trace port interface unit (TPIU)
  • Boot from FPGA interface
Figure 160. HPS BFM Block Diagram

The HPS BFMs use standard function calls from the BFM application programming interface (API), as detailed in the remainder of this chapter.

HPS simulation supports only Verilog HDL or SystemVerilog simulation environments. Users with VHDL Custom IP can run BFM simulations so long as a mixed-language simulation license is available on their chosen simulator.