Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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3.3.4. Hardware Sequenced Clock Groups

The hardware sequenced clock groups consists of the MPU clocks and the NOC clocks. The following diagram shows the external bypass muxes, hardware-managed external counters and dividers, and clock gates. For hardware-managed clocks, the group of clocks has only one software enable for the clock gate. As a result, the group of clocks are all enabled or disabled together. The slight exception is the NOC has two software enables, one for the l3/l4 clocks and one for the CoreSight clocks.

Figure 7. Hardware Clock Groups


Table 14.  The Hardware Sequenced Clocks Feature Summary
Clock Output Group System Clock Name Frequency Boot Frequency Uses
MPU mpu_clk PLL C0 boot_clk MPU subsystem, including CPU0 and CPU1
mpu_I2_ram_clk mpu_clk/2 boot_clk MPU level 2 (L2) RAM
mpu_periph_clk mpu_clk/4 boot_clk MPU snoop control unit (SCU) peripherals, such as the general interrupt controller (GIC)
NOC l3_main_free_clk PLL C1 boot_clk L3 interconnect
l4_sys_free_clk l3_main_free_clk/4 boot_clk/2 L4 interconnect
l4_sys_free_div4_clk l4_sys_free_clk/4 l4_sys_free_clk/4 L4 interconnect timer reference
l4_main_clk l3_main_free_clk/{1,2,4,8} boot_clk L4 main bus
l4_mp_clk l3_main_free_clk/{1,2,4,8} boot_clk L4 MP bus
l4_sp_clk l3_main_free_clk/{1,4,8} boot_clk/2 L4 SP bus
cs_timer_clk l3_main_free_clk/{1,2,4,8} boot_clk Trace timestamp generator
cs_at_clk l3_main_free_clk/{1,2,4,8} boot_clk CoreSight debug trace bus
cs_pdbg_clk cs_at_clk/{1,4} cs_at_clk/2 Debug Access Port (DAP) and debug peripheral bus
cs_trace_clk cs_at_clk/{1,2,8} cs_at_clk/4 Coresight debug Trace Port Interface Unit (TPIU)
Main FPGA Reference h2f_user0_clk h2f_user0_free_clk boot_clk FPGA