Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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Document Table of Contents

28.2.1. General Interfaces

When enabled, the interfaces described in the following table become visible in the HPS component.

Table 227.  General Parameters

Parameter Name

Parameter Description

Interface Name

Enable MPU standby and event signals

Enables interfaces that perform the following functions:

  • Notify the FPGA fabric that the microprocessor unit (MPU) is in standby mode.
  • Wake up an MPCore processor from a wait for event (WFE) state.

h2f_mpu_events

Input for FPGA to signal events to both processors. This signal must be asserted high for at least two MPU clock cycles to be visible to either Cortex*-A9 processor core. This signal is used to wake either processor core from standby mode.

h2f_mpu_eventi

Output event from either processor sent to the FPGA. The output event is a multiple cycle pulse so logic in the FPGA should detect it using a rising edge detector circuit to detect the occurrence of the event. This signal is asserted each time either processor executes the SEV instruction.

h2f_mpu_evento

Output per processor that indicates if the processor is in WFE standby mode. When high the processor is in WFE standby mode.

h2f_mpu_standbywfe [1..0]

Output per processor that indicates if the processor is in WFI standby mode. When high the processor is in WFI standby mode.

h2f_mpu_standbywfi [1..0]

Enable general purpose signals

Enables a pair of 32‑bit unidirectional general‑purpose interfaces between the FPGA fabric and the FPGA manager in the HPS portion of the SoC device.

h2f_gp

  • h2f_gp_in [31..0]
  • h2f_gp_out [31..0]

Enable Debug APB* interface

Enables debug interface to the FPGA, allowing access to debug components in the HPS. For more information, refer to the CoreSight Debug and Trace chapter.
h2f_debug_apb
  • h2f_dbg_apb_PADDR [17..0]
  • h2f_dbg_apb_PADDR31
  • h2f_dbg_apb_PENABLE
  • h2f_dbg_apb_PRDATA [31..0]
  • h2f_dbg_apb_PREADY
  • h2f_dbg_apb_PSEL
  • h2f_dbg_apb_PSLVERB
  • h2f_dbg_apb_PWDATA [31..0]
  • h2f_dbg_apb_PWRITE
h2f_debug_apb_sideband
  • h2f_debug_apb_PCLKEN
  • h2f_debug_apb_DBG_APB_DISABLE
h2f_debug_apb_clock
  • h2f_abg_apb_clk
h2f_debug_apb_reset
  • h2f_dbg_apb_rst_n

Enable System Trace Macrocell hardware events

Enables system trace macrocell (STM) hardware events, allowing logic inside the FPGA to insert messages into the trace stream. For more information, refer to the CoreSight Debug and Trace chapter.

f2h_stm_hw_events

  • f2h_stm_hwevents [27..0]

Enable FPGA Cross Trigger interface

Enables the cross trigger interface (CTI), which allows trigger sources and sinks to interface with the embedded cross trigger (ECT). For more information, refer to the CoreSight Debug and Trace chapter.

If this interface has to be connected to a SignalTap II instance in the FPGA fabric, then it has to be left disabled in Platform Designer (Standard).

h2f_cti

  • h2f_cti_trig_in [7..0]
  • h2f_cti_trig_out_ack [7..0]
  • h2f_cti_trig_out [7..0]
  • h2f_cti_trig_in_ack [7..0]

Enable boot from FPGA signals

Enables an input to the HPS indicating whether a preloader is available in the on-chip memory of the FPGA. This option also enables a separate input to the HPS indicating a fallback preloader is available in the FPGA memory. A fallback preloader is used when there is no valid preloader image found in flash memory.

For more information, refer to Appendix A: Booting and Configuration.

f2h_boot_from_fpga

This is an active high signal which the Boot ROM polls to determine when the FPGA is configured and the memory located at offset 0x0 from the FPGA to HPS bridge is ready to be written to. When the FPGA is not configured the hardware drives this signal low. You will need to drive this signal high when the memory in the FPGA is ready to accept memory mapped transactions.

The f2h_boot_from_fpga_ready signal is used by the Boot ROM when accessing the public key stored in the FPGA. The Boot ROM will only use the signal if asserted to boot with the public key.

For more information, refer to Appendix A: Booting and Configuration.

f2h_boot_from_fpga_ready

This is an active high signal which the Boot ROM polls when all the preloaders fail to load. This signal is driven low when the FPGA is not configured. You will need to drive the signal high in your design. The Boot ROM will continuously poll both f2h_boot_from_fpga signals until both are set.

For more information, refer to Appendix A: Booting and Configuration.

f2h_boot_from_fpga_on_failure