Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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A.4.3.1. Boot Source I/O Pins

The HPS has 17 dedicated I/O pins. Three are used as a clock, cold reset and warm reset pin. The warm reset signal is a bidirectional signal; a warm reset event can drive into the HPS, or a warm reset event can be generated by the HPS and drive out of this pin.

The remaining 14 dedicated I/O pins are used for boot devices as well as other peripherals. Three of these 14 dedicated I/O pins are sampled by software at either cold or warm reset and convey boot source information. The following table identifies the pin mux values for the boot source options.

Table 309.   Boot Source MUX Selects This table identifies the dedicated HPS signals that are mapped to each boot interface and the mux select value each boot interface signal requires. Note that Clock Manager clock inputs are also assigned to MUX select 4 and are documented here for thoroughness.

Signal

MUX Select
14 8 4
HPS_DEDICATED_4 NAND_ADQ0 SDMMC_DATA0 QSPI_CLK
HPS_DEDICATED_5 NAND_ADQ1 SDMMC_CMD QSPI_IO0
HPS_DEDICATED_6/BOOTSEL2 NAND_WE_N SDMMC_CCLK QSPI_SS0
HPS_DEDICATED_7 NAND_RE_N SDMMC_DATA1 QSPI_IO1
HPS_DEDICATED_8 NAND_ADQ2 SDMMC_DATA2 QSPI_IO2_WPN
HPS_DEDICATED_9 NAND_ADQ3 SDMMC_DATA3 QSPI_IO3_HOLD
HPS_DEDICATED_10/BOOTSEL1 NAND_CLE SDMMC_PWR_ENA
HPS_DEDICATED_11/BOOTSEL0 NAND_ALE QSPI_SS1
HPS_DEDICATED_12 NAND_RB SDMMC_DATA4
HPS_DEDICATED_13 NAND_CE_N SDMMC_DATA5
HPS_DEDICATED_14 NAND_ADQ4 SDMMC_DATA6
HPS_DEDICATED_15 NAND_ADQ5 SDMMC_DATA7
HPS_DEDICATED_16 NAND_ADQ6 QSPI_SS2
HPS_DEDICATED_17 NAND_ADQ7 QSPI_SS3
Note: The MUX selects for the QSPI interface signals include both mux select 4 and mux select 8.
Table 310.   Boot Source MUX Selects (Alternate View)This table displays the same information as the prior table but as an alternative view per interface selected. The number in each cell shows the mux select value needed to select the correct interface signal on the pin

Signal

Boot Interface
NAND SDMMC QSPI
HPS_DEDICATED_4 14 8 4
HPS_DEDICATED_5 14 8 4
HPS_DEDICATED_6/BOOTSEL2 14 8 4
HPS_DEDICATED_7 14 8 4
HPS_DEDICATED_8 14 8 4
HPS_DEDICATED_9 14 8 4
HPS_DEDICATED_10/BOOTSEL1 14 8 Not Used
HPS_DEDICATED_11/BOOTSEL0 14 Not Used 8
HPS_DEDICATED_12 14 8 Not Used
HPS_DEDICATED_13 14 8 Not Used
HPS_DEDICATED_14 14 8 Not Used
HPS_DEDICATED_15 14 8 Not Used
HPS_DEDICATED_16 14 Not Used 8
HPS_DEDICATED_17 14 Not Used 8