Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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A.7.2. Early I/O Release FPGA Configuration Flow Through HPS

Figure 181. Early I/O Release FPGA Configuration Flow Through HPSThe I/Os are configured and the shared and hard memory controller I/Os are released so that the HPS has immediate access to them. The FPGA fabric configuration follows at a later time.
Note: The FPGA fabric is not required to be programmed immediately after the first I/O configuration. You can also program the I/Os, re-program the I/Os and then program the FPGA fabric as long as the early I/O release configuration option is enabled in each I/O configuration file.
Note: If you are using the early I/O release configuration flow, you cannot initially use SmartVID to power your device. Instead, you can use a fixed power supply until after the FPGA is configured. When the FPGA is configured, you can then enable SmartVID.
You can enable early I/O configuration in Intel® Quartus® Prime:
  1. Click on the the Assignments menu and select Device.
  2. When the Device settings window opens, click the Device and Pin Options button.
  3. In the General category, click on the option labeled "Enables the HPS early release of HPS IO".
Figure 182.  Intel® Quartus® Prime Early I/O Release Setting