Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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8.3.3.2. Sharing I/Os between the EMIF and the FPGA

Arria 10 SoC devices have three modular I/O banks to connect the HPS to an SDRAM (2K, 2J, and 2I) through a dedicated HPS EMIF.

Each bank has four I/O lanes that correspond to:

  • Lane 3: IO[47:36]
  • Lane 2: IO[35:24]
  • Lane 1: IO[23:12]
  • Lane 0: IO[11:0]
Figure 38. HPS Hard Memory Controller

To use SDRAM, you instantiate the HPS EMIF in Platform Designer, by selecting the Arria 10 External Memory Interfaces for HPS component. Quartus Prime software assigns the correct banks and lanes for the SDRAM I/O.

I/Os in these three banks can be shared between the HPS EMIF and FPGA. Quartus Prime software enforces the following guidelines on shared I/Os:

  • Modular I/O banks 2K, 2J and 2I can be used entirely as FPGA GPIO when there is no HPS EMIF in the system.
  • Bank 2K:
    • If there is an HPS EMIF in the system, lane 3 is used for ECC for the SDRAM. Unused pins in lane 3 may be used as FPGA inputs only.
    • Lanes 2, 1, and 0 are used for address and command for the SDRAM. Unused pins in these lanes may be used as FPGA inputs or outputs.
  • Bank 2J:
    • If there is an HPS EMIF in the system, bank 2J is used for data bits [31:0].
      • With 16-bit data widths, unused pins in the two lanes of bank 2J used for data can be used as inputs only. The pins in the remaining two lanes can be used as FPGA inputs or outputs.
      • With 32-bit data widths, unused pins bank 2J can be used as FPGA inputs only.
  • Bank 2I:
    • If there is an HPS EMIF in the system, bank 2I is used for data bits [63:32]
      • With 64-bit data widths, unused pins in bank 2I can be used as FPGA inputs only.
      • With 32- or 16-bit data widths, bank 2I can be used as FPGA inputs or outputs.