Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.2.11.1. QoS Generators in the Interconnect Architecture

The principal masters into the system interconnect are equipped with QoS generators.

The following table shows the interconnect initiators (masters) that support QoS generation.

Table 55.  QoS Generators on Interconnect Masters
Master Name(s) Default QoS Generator Mode Clock
MPU Subsystem L2 cache M0/1 Limiter mpu_l2ram_clk
FPGA-to-HPS Bridge Limiter fpga2hps_clk
FPGA-to-SDRAM Ports Regulator f2h_sdram_clk
DMA Limiter l4_main_clk
EMAC 0/1/2 Regulator l4_mp_clk
USB OTG 0/1 Regulator l4_mp_clk
NAND Regulator l4_mp_clk
SD/MMC Regulator l4_mp_clk