Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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8.3.2.2. Memory Timing Configuration

The SDRAM L3 interconnect provides fully-programmable timing parameter support for all JEDEC-specified timing parameters.

The following lists the handoff information used to control the SDRAM scheduler:

  • The scheduler is aware of the SDRAM timing so that it can guide traffic into the hard memory controller.
  • This information is not used to control the subsystem that sets up memory timings in the hard memory controller hardware.