Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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8.3.2.1. FPGA Port Configuration

The FPGA has three outputs that pass through the firewall before connecting to the SDRAM scheduler.

You can configure the FPGA-to-SDRAM (F2SDRAM) ports to data widths of 32, 64, or 128 bits:

  • F2SDRAM 0 - 32-, 64-, or 128-bit data widths
  • F2SDRAM 1 - 32- or 64-bit data widths
  • F2SDRAM 2 - 32-, 64-, or 128-bit data widths
There are four port configurations that are a combination of the SDRAM ports 0 - 2 that you are able to select. Once a port configuration is selected, you can choose to disable ports that you do not need.
Note: The total data width of all interfaces is limited to a maximum of 256 bits in the read direction and 256 bits in the write direction.
Port Configuration F2SDRAM 0 F2SDRAM 1 F2SDRAM 2
1 32-bit 32-bit 32-bit
2 64-bit 64-bit 64-bit
3 128-bit unused 128-bit
4 128-bit 32-bit 64-bit