Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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13.4.2. Warm Reset Sequence

  1. You can assert warm reset request using the EL3 register via software. You must ensure that all CPUs enter WFI mode (for example, consider CPU0 is the master CPU):
    1. CPU3/2/1 interrupt routine:
      1. Pause all transaction prior to interrupt.
      2. Idle the CPU3/2/1 with the WFI mode.
    2. CPU0 interrupt routine:
      1. Pause all transaction prior to interrupt.
      2. Perform L2FLUSH.
      3. Set the SDRSELFREFREQ to request that the SDRAM Controller Subsystem to stop accepting any new transactions and allows all outstanding transactions to drain.
      4. Write to EL3 register to reset.
      5. Idle the CPU0 with the WFI mode.
  2. Reset Manager performs the following handshakes:
    1. HMC handshaking, if enabled using the hdsken register.
    2. FPGA handshaking, if enabled using the hdsken register.
    3. ETR handshaking, if enabled using the hdsken register.
  3. Reset Manager initiates boot mode request handshake with Clock Manager.
  4. Reset Manager waits for an acknowledgement signal from Clock Manager that indicates completion of the boot mode handshake before proceeding any further.
    • A cold or watchdog reset request that occurs before the completion of this step takes precedence over the warm reset sequence.
    • A cold or watchdog reset request that occurs after the completion of this step is delayed until the warm reset is completed.
  5. Reset Manager asserts System Warm Reset. After a definite time-period, Reset Manager de-asserts all modules in reset except MPU.
  6. Reset Manager waits until the ocramload.done bit is set.
  7. Reset Manager de-asserts L2/SCU using the coldmodrst.l2 register bit.
  8. Reset Manager de-asserts MPU cores using the mpumodrst.core[3:0] and coldmodrst.cpupor[3:0] register bits.
  9. You can de-assert peripheral modules using the per0modrst and per1modrst registers.