Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

25.5.1. CoreSight Component Address

CoreSight components are configured through memory-mapped registers, located at offsets relative to the CoreSight component base address. CoreSight component base addresses are accessible through the component address table in the DAP ROM.

Table 223.  CoreSight Component Address TableThe following table is located in the ROM table portion of the DAP.

ROM Entry

Offset[30:12]

Description

0x0

0x00001

ETF Component Base Address

0x1

0x00002

CTI Component Base Address

0x2

0x00003

TPIU Component Base Address

0x3

0x00004

Trace Funnel Component Base Address

0x4

0x00005

STM Component Base Address

0x5

0x00006

ETR Component Base Address

0x6

0x00007

FPGA-CTI Component Base Address

0x7

0x00008

NOC-CTI

0x8

0x00008

ATBREPLICATOR

0x9

0x0000A

TS

0xA

0x0000B

GT-CTI

0xB

0x00080

FPGA ROM

0xC

0x00400

A53 ROM

0xD

0x00000

End of ROM

A host debugger can access this table at 0x80000000 through the DAP. HPS masters can access this ROM at 0xFF000000. Registers for a particular CoreSight component are accessed by adding the register offset to the CoreSight component base address, and adding that total to the base address of the ROM table.