Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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15.4.9.1.1. Command-Data Pair Formats

Table 116.  Command-Data Pair 1
  31:28 27:26 25:24 23:<M> 26 (<M> – 1):0
(<M> – 1):0 0x0 0x2 0x0 Block address Page address
Note: <M> = ceil(log2(<device pages per block>)). Therefore, use the following values:
  • 32 pages per block: <M>=5
  • 64 pages per block: <M>=6
  • 128 pages per block: <M>=7
  • 256 pages per block: <M>=8
  • 384 pages per block: <M>=9
  • 512 pages per block: <M>=9
  31:16 15:12 11:8 7:0
Data 0x0 0x2

0x0 = Read

0x1 = Write

<PP>= Number of pages
Table 117.  Command-Data Pair 2
  31:28 27:26 25:24 23:8 7:0
Command 0x0 0x2 0x0 Memory address high 0x0
  31:16 15:12 11:8 7:0
Data 0x0 0x2 0x2 0x0
Table 118.  Command-Data Pair 3
  31:28 27:26 25:24 23:8 7:0
Command 0x0 0x2 0x0 Memory address low27 0x0
  31:16 15:12 11:8 7:0
Data 0x0 0x2 0x3 0x0
Table 119.  Command-Data Pair 4
  31:28 27:26 25:24 23:17 16 15:8 7:0
Command 0x0 0x2 0x0 0x0 INT Burst length 0x0
Note: INT specifies the host interrupt that is generated at the end of the complete DMA transfer; and controls the value of the dma_cmd_comp bit of the intr_status0 register in the status group at the end of the DMA transfer. INT can take on one of the following values:
  • 0—Do not interrupt host. The dma_cmd_comp bit is set to 0.
  • 1—Interrupt host. The dma_cmd_comp bit is set to 1.
  31:16 15:12 11:8 7:0
Data 0x0 0x2 0x4 0x0
26 <M> depends on the number of pages per block in the device. For more information about <M>, see the Note at the bottom of this table.
27 The buffer address in host memory, which must be aligned to a 4-byte boundary.