Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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B.2. Taking Ownership of Quad SPI Controller

On power up, the SDM owns the quad SPI controller. In order for the HPS to use the quad SPI Controller, it has to request ownership from the SDM.

The following details the typical flow for the HPS to use the quad SPI:
  1. The Bootloader (either U-Boot or UEFI) is configured to use quad SPI, and takes control of the quad SPI from the SDM. The SDM resets the quad SPI controller and reports back to the bootloader the value of the quad SPI reference clock.
  2. The bootloader passes the value of the quad SPI Controller reference clock to the end application or operating system.
  3. The end application uses the quad SPI controller.

For the Linux* use case, the U-Boot passes the value of the quad SPI reference clock into the Linux device tree. The HPS cannot reset the quad SPI controller, gate its clocks, nor use the DMA for quad SPI transfers; it can only obtain ownership of the quad SPI controller when the MSEL pins are configured to select quad SPI for SDM configuration. Quad SPI pin-muxing is configured in the Intel® Quartus® Prime project, and cannot be changed by the HPS.