Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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11.3.2. PLL Integration

The two PLLs contain exactly the same set of output clocks. PLL0 is intended to be used for the MPU and Interconnect clocks. PLL1 outputs are routed to the HPS master peripherals.

Figure 30. PLL Integration in Clock Manager
Table 95.  PLL Direct OutputsFor Boot mode, the maximum and minimum frequency is 200 MHz and 10 MHz respectively.
PLL Output Counter Clock Name
Main PLL C0 pll_main_c0
C1 pll_main_c1
C2 pll_main_c2
C3 pll_main_c3
Peripheral PLL C0 pll_peri_c0
C1 pll_peri_c1
C2 pll_peri_c2
C3 pll_peri_c3
Note: The clock slice outputs of both the Main and Peripheral PLL are disabled out of reset.