Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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25.4.9.2. Cross Trigger Matrix

A CTM is a transport mechanism for triggers traveling from one CTI to one or more CTIs or CTMs. The HPS contains two CTMs. One CTM connects CTI, FPGA-CTI, and MPU-CTM; the other connects CTI-NOC. The two CTMs are connected together, allowing triggers to be transmitted between the MPU debug subsystem, the debug system, and the FPGA fabric.

The following describes the inputs and outputs for the CTM.
Table 217.  Cross Trigger Matrix Connections for CS CTM
Name Source/Destination Description
CTM channel input – Port 0 CTI This data is in the CTI clock domain and can be synchronized.
CTM channel output – Port 0 CTI Its output is synchronized to the CTM clock domain. The CTI can enable the clock domain synchronizers.
CTM channel input – Port 1 MPU-CTM This data is in the MPU-CTM clock domain and can be synchronized.
CTM channel output – Port 1 MPU-CTM Its output is synchronized to the MPU-CTM clock domain. The MPU-CTM can enable clock domain synchronizers.
CTM channel input – Port 2 FPGA-CTI This data is in the FPGA-CTI clock domain and can be synchronized.
CTM channel output – Port 2 FPGA-CTI Its output is synchronized to the FPGA-CTI clock domain. The FPGA-CTI can enable clock domain synchronizers.
CTM channel input – Port 3 CS CTM This data is in the MPU-CTM clock domain and can be synchronized.
CTM channel output – Port 3 CS CTM Its output is synchronized to the MPU-CTM clock domain. The CS CTM can enable clock domain synchronizers.

For more information, refer to the CoreSight Components Technical Reference Manual on the ARM® Infocenter website.