Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

16.5.5.2. Busy Signal After CE-ATA RW_BLK Write Transfer

During CE‑ATA RW_BLK write transfers, the MMC busy signal might be asserted after the last block. If the CE‑ATA card device interrupt is disabled (the nIEN bit in the card device’s ATA control register is set to 1), the dto bit in the rintsts register is set to 1 even though the card sends MMC BUSY. The host cannot issue the CMD60 command to check the ATA busy status after a CMD61 command. Instead, the host must perform one of the following actions:
  • Issue the SEND_STATUS command and check the MMC busy status before issuing a new CMD60 command
  • Issue the CMD39 command and check the ATA busy status before issuing a new CMD60 command

For the data transfer commands, software must set the ctype register to the bus width that is programmed in the card.