Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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19.5.5.2. Example: Slave Selection Software Flow for SPI Slave

  1. If the SPI slave is enabled, disable it by writing 0 to SPIENR.
  2. Write CTRLR0 to match the required transfer.
  3. Write TXFTLR and RXFTLR to set FIFO buffer threshold levels.
  4. Write IMR register to set interrupt masks.
  5. Write SPIENR register bit 0 to 1 to enable SPI slave.
  6. If the SPI slave transmits data, write data into TX FIFO buffer.
    Note: All other SPI slaves are disabled (SPIENR = 0) and therefore is not respond to an active level on their ss_in_n port.

The FIFO buffer depth (FIFO_DEPTH) for both the RX and TX buffers in the SPI controller is 256 entries.