Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

14.4. Intel® Agilex™ Pin MUX Test Considerations

The HPS dedicated I/O pins are chained into the full chip JTAG boundary scan chain.

In some power modes the HPS can be off or disabled. However, the boundary scan chain still includes the HPS dedicated I/O pins, even when the HPS is inactive.

While the boundary scan is taking place, you must ensure that no software is executing in the HPS.

Note: You can only perform boundary scan with the FPGA JTAG. HPS JTAG does not support boundary scan.