Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1. Functional Description

The system interconnect consists of connection points, datapaths, and the service network.
  • Connection points interface the Interconnect to masters and slaves of other HPS components.
  • Datapath switches transport data across the network, from initiator connection points to target connection points.
  • Service network allows you to update master and slave peripheral security features and access Interconnect registers.

The system interconnect is also connected to the Cache Coherency Unit (CCU). The CCU provides additional routing between the MPU, FPGA-to-HPS bridge, MPFE, GIC, and on-chip RAM.

In addition to providing routing connectivity and arbitration between masters and slaves in the HPS, the system interconnect also features firewall security, QoS mechanisms, and observation probe points.
Figure 9. Block Diagram
The system interconnect has a transaction-based architecture that functions as a partially-connected fabric. Not all masters can access all slaves.

Each system interconnect packet carries a transaction between a master and a slave. The interconnect provides interface widths up to 128 bits, connecting to the L4 slave buses and to HPS and FPGA masters and slaves.

The system interconnect provides low-latency connectivity to the following interfaces:

  • HPS-to-FPGA bridge
  • Lightweight HPS-to-FPGA bridge
  • FPGA-to-HPS bridge