Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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7.5.1. Lightweight HPS-to-FPGA Bridge Signals

Table 82.  Lightweight HPS-to-FPGA Bridge Signals
Name Direction Description
h2f_lw_axi_clock Input Clock source from FPGA.
h2f_lw_axi_reset Input Module reset signal from Reset Manager.
lwsoc2fpga_port_size_config[0] Input Port width configuration signal from FPGA:
  • 0: 32-bit
  • 1: Reserved