Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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15.5.1.6.1. Order of Interrupt Status Bits Assertion

The following interrupt status bits, in the intr_status0 register in the status group, are listed in the order of interrupt bit setting:
  1. time_out—All other interrupt bits are set to 0 when the watchdog time_out bit is asserted.
  2. dma_cmd_comp—This bit signifies the completion of data transfer sequence.29
  3. pipe_cpybck_cmd_comp—This bit is asserted when a copyback command or the last page of a pipeline command completes.
  4. locked_blk—This bit is asserted when a program (or erase) is performed on a locked block.
  5. INT_act—No relationship with other interrupt status bits. Indicates a transition from 0 to 1 on the ready_busy pin value for that flash device.
  6. rst_comp—No relationship with other interrupt status bits. Occurs after a reset command has completed.
  7. For an erase command:
    1. erase_fail (if failure)
    2. erase_comp
  8. For a program command:
    1. locked_blk (if performed on a locked block)
    2. pipe_cmd_err (if the pipeline sequence is broken by a MAP01 command)
    3. page_xfer_inc (at the end of each page data transfer)
    4. program_fail (if failure)
    5. pipe_cpybck_cmd_comp
    6. program_comp
    7. dma_cmd_comp (If DMA enabled)
  9. For a read command:
    1. pipe_cmd_err (if the pipeline sequence is broken by a MAP01 command)
    2. page_xfer_inc (at the end of each page data transfer)
    3. pipe_cpybck_cmd_comp
    4. load_comp
    5. ecc_uncor_error (if failure)
    6. dma_cmd_comp (If DMA enabled)
29 This interrupt status bit is the last to be asserted during a DMA operation to transfer data.