Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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4.2.2. System Integration

Figure 5. Cache Coherency Unit Integration Within System

The coherency interconnect in the CCU accepts both coherent and non-coherent transactions from masters in the system. The coherency interconnect routes non-coherent transactions to the appropriate target.

All accesses from the Cortex® -A53 MPCore™ are routed through the CCU so the coherency directory can be updated. TCU and FPGA-to-HPS bridge accesses and peripheral master accesses coming from the L3 interconnect are routed to the CCU if they are cacheable. Non-cacheable accesses route directly to the slave.

Note: As part of the SMMU, translation buffer units (TBUs) sit between the master peripherals and the L3 interconnect. The FPGA-to-HPS bridge interface also passes through a TBU before interfacing with the CCU. The system TCU manages the TBUs and performs page table walks on translation misses. A DVM interface on the TCU allows the Cortex-A53 MPCore™ processor to send TLB control information to the TCU.

The CCU interfaces with the L3 interconnect and the MPFE. The MPFE provides a 32-bit register bus interface to the CCU for accessing the MPFE interconnect and hard memory controller. The CCU accesses external memory through a 512-bit interface to the MPFE.