Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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2.2.6. System Interconnect

The system interconnect supports the following features:
  • Configurable ARM® TrustZone* -compliant firewall and security support.
    • For each peripheral, implements secure or non-secure access.
    • Allows configuration of individual transactions as secure or non-secure at the initiating master.
  • Multi-tiered bus structure to separate high bandwidth masters from lower bandwidth peripherals and control and status ports.
  • Quality of service (QoS) with three programmable levels of service on a per masterbasis.
  • On-chip debugging and tracing capabilities. The system interconnect is based on the Arteris® FlexNoC™ network-on-chip (NoC) interconnect technology.