Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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3.5.3. Memory Management Unit

Each CPU of the Cortex® -A53 MPCore™ contains a memory management unit (MMU) that translates virtual addresses to physical addresses. Address mappings and memory attributes are held in page tables that are loaded into the translation lookaside buffer (TLB) when a location is accessed.

The MMUs support 40-bit physical address size and two stages of translation. You can enable or disable each stage of address translation independently.

The Cortex® -A53 MPCore™ communicates with the system memory management unit (SMMU) when pages are invalidated in a CPU's MMU.

For more information regarding the SMMU, refer to the System Memory Management Unit chapter.