Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

16.4.2.5.3. Internal DMA Controller Descriptor Fields

The DES0 field in the internal DMA controller descriptor contains control and status information.

Table 130.  Internal DMA Controller DES0 Descriptor Field
Bits Name Description

31

OWN

When set to 1, this bit indicates that the descriptor is owned by the internal DMA controller.

When this bit is set to 0, it indicates that the descriptor is owned by the host. The internal DMA controller resets this bit to 0 when it completes the data transfer.

30

Card Error Summary (CES)

The CES bit indicates whether a transaction error occurred. The CES bit is the logical OR of the following error bits in the rintsts register.

  • End‑bit error (ebe)
  • Response timeout (rto)
  • Response CRC (rcrc)
  • Start‑bit error (sbe)
  • Data read timeout (drto)
  • Data CRC for receive (dcrc)
  • Response error (re)

29:6

Reserved

5

End of Ring (ER)

When set to 1, this bit indicates that the descriptor list reached its final descriptor. The internal DMA controller returns to the base address of the list, creating a descriptor ring. ER is meaningful for only a dual‑buffer descriptor structure.

4

Second Address Chained (CH)

When set to 1, this bit indicates that the second address in the descriptor is the next descriptor address rather than the second buffer address. When this bit is set to 1, BS2 (DES1[25:13]) must be all zeros.

3

First Descriptor (FD)

When set to 1, this bit indicates that this descriptor contains the first buffer of the data. If the size of the first buffer is 0, next descriptor contains the beginning of the data.

2

Last Descriptor (LD)

When set to 1, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the data.

1

Disable Interrupt on Completion (DIC)

When set to 1, this bit prevents the setting of the TI/RI bit of the internal DMA controller status register (idsts) for the data that ends in the buffer pointed to by this descriptor.

0

Reserved

Table 131.  Internal DMA Controller DES1 Descriptor Field The DES1 descriptor field contains the buffer size.
Bits Name Description

31:26

Reserved

25:13

Buffer 2 Size (BS2)

This field indicates the second data buffer byte size. The buffer size must be a multiple of four. When the buffer size is not a multiple of four, the resulting behavior is undefined. This field is not valid if DES0[4] is set to 1.

12:0

Buffer 1 Size (BS1)

Indicates the data buffer byte size, which must be a multiple of four bytes. When the buffer size is not a multiple of four, the resulting behavior is undefined. If this field is 0, the DMA ignores the buffer and proceeds to the next descriptor for a chain structure, or to the next buffer for a dual‑buffer structure.

If there is only one descriptor and only one buffer to be programmed, you need to use only buffer 1 and not buffer 2.

Table 132.  Internal DMA Controller DES2 Descriptor Field The DES2 descriptor field contains the address pointer to the data buffer.
Bits Name Description

31:0

Buffer Address Pointer 1 (BAP1)

These bits indicate the physical address of the first data buffer. The internal DMA controller ignores DES2 [1:0], because it only performs 32‑bit aligned accesses.

Table 133.  Internal DMA Controller DES3 Descriptor Field The DES3 descriptor field contains the address pointer to the next descriptor if the present descriptor is not the last descriptor in a chained descriptor structure or the second buffer address for a dual‑buffer structure.
Bits Name Description

31:0

Buffer Address Pointer 2 (BAP2) or Next Descriptor Address

These bits indicate the physical address of the second buffer when the dual‑buffer structure is used. If the Second Address Chained (DES0[4]) bit is set to 1, this address contains the pointer to the physical memory where the next descriptor is present.

If this is not the last descriptor, the next descriptor address pointer must be aligned to 32 bits. Bits 1 and 0 are ignored.