Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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3.5.11. Abort Handling

The following list details items you should take into consideration about abort handling.

  • All load accesses synchronously abort.
  • All STREX, STREXB, STREXH, STREXD, STXR, STXRB, STXRH, STXP, STLXR, STLXRB, STLXRH and STLXP instructions use the synchronous abort mechanism.
  • All store accesses to device memory, or normal memory that is inner non-cacheable, inner write-through, outer non-cacheable, or outer write-through use the asynchronous abort mechanism, except for STREX, STREXB, STREXH, STREXD, STXR, STXRB, STXRH, STXP, STLXR, STLXRB, STLXRH, and STLXP.
  • All store accesses to normal memory that is both inner cacheable and outer cacheable and any evictions from L1 or L2 cache do not cause an abort in the processor. Instead, an nEXTERRIRQ interrupt is asserted because the access that aborts might not relate directly back to a specific CPU in the cluster.
  • L2 linefills triggered by an L1 Instruction fetch assert the nEXTERRIRQ interrupt if the data is received from the interconnect in a dirty state. Instruction data can be marked as dirty as a result of self-modifying code or a line containing a mixture of data and instructions. If an error response is received on any part of the line, the dirty data might be lost.
Note: When nEXTERRIRQ is asserted it remains asserted until the error is cleared by a write of 0 to the AXI asynchronous error bit of the L2ECTLR register.