Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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17.6.2.6. Reception

Receive functions use receive descriptors. The following steps are reception sequence for receive DMA engine:
  1. The host sets up receive descriptors (RDES0‑RDES3) and sets the Own bit (RDES0[31]).
  2. When Bit 1 (SR) of Register 6 (Operation Mode Register) is set, the DMA enters the Run state. While in the Run state, the DMA polls the receive descriptor list, attempting to acquire free descriptors. If the fetched descriptor is not free (is owned by the host), the DMA enters the Suspend state and jumps to 9.
  3. The DMA decodes the receive data buffer address from the acquired descriptors.
  4. Incoming frames are processed and placed in the acquired descriptor’s data buffers.
  5. When the buffer is full or the frame transfer is complete, the receive engine fetches the next descriptor.
  6. If the current frame transfer is complete, the DMA proceeds to 7. If the DMA does not own the next fetched descriptor and the frame transfer is not complete (EOF is not yet transferred), the DMA sets the Descriptor Error bit in the RDES0 (unless flushing is disabled in Bit 24 of Register 6 (Operation Mode Register)). The DMA closes the current descriptor (clears the Own bit) and marks it as intermediate by clearing the Last Segment (LS) bit in the RDES0 value (marks it as Last Descriptor if flushing is not disabled), then proceeds to 8. If the DMA does own the next descriptor but the current frame transfer is not complete, the DMA closes the current descriptor as intermediate and reverts to 4.
  7. If IEEE 1588 timestamping is enabled, the DMA writes the timestamp (if available) to the current descriptor’s RDES2 and RDES3. It then takes the receive frame’s status from the MTL and writes the status word to the current descriptor’s RDES0, with the Own bit cleared and the Last Segment bit set.
  8. The receive engine checks the latest descriptor’s Own bit. If the host owns the descriptor (Own bit is 0), the Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set and the DMA receive engine enters the Suspended state (Step 9). If the DMA owns the descriptor, the engine returns to 4 and awaits the next frame.
  9. Before the receive engine enters the Suspend state, partial frames are flushed from the receive FIFO buffer. You can control flushing using Bit 24 of Register 6 (Operation Mode Register). 
  10. The receive DMA exits the Suspend state when a Receive Poll demand is given or the start of next frame is available from the MTL’s receive FIFO buffer. The engine proceeds to 2 and refetches the next descriptor. 
Figure 70. Receive DMA Operation

When software has enabled timestamping through the tsena bit of register 448 (Timestamp Control Register) and a valid timestamp value is not available for the frame (for example, because the receive FIFO buffer was full before the timestamp could be written to it), the DMA writes all ones to RDES2 and RDES3 descriptors. Otherwise (that is, if timestamping is not enabled), the RDES2 and RDES3 descriptors remain unchanged.