Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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16.5.11. Interrupt and Error Handling

This section describes how to use interrupts to handle errors. On power‑on or reset, interrupts are disabled (the int_enable bit in the ctrl register is set to 0), and all the interrupts are masked (the intmask register default is 0). The controller error handling includes the following types of errors:
  • Response and data timeout errors—For response time‑outs, the host software can retry the command. For data time‑outs, the controller has not received the data start bit from the card, so software can either retry the whole data transfer again or retry from a specified block onwards. By reading the contents of the tcbcnt register later, the software can decide how many bytes remain to be copied (read).
  • Response errors—Set to 1 when an error is received during response reception. If the response received is invalid, the software can retry the command.
  • Data errors—Set to 1 when a data receive error occurs. Examples of data receive errors:
    • Data CRC
    • Start bit not found
    • End bit not found

    These errors can be occur on any block. On receipt of an error, the software can issue an SD/SDIO STOP or SEND_IF_COND command, and retry the command for either the whole data or partial data.

  • Hardware locked error—Set to 1 when the controller cannot load a command issued by software. When software sets the start_cmd bit in the cmd register to 1, the controller tries to load the command. If the command buffer already contains a command, this error is raised, and the new command is discarded, requiring the software to reload the command.
  • FIFO buffer underrun/overrun error—If the FIFO buffer is full and software tries to write data to the FIFO buffer, an overrun error is set. Conversely, if the FIFO buffer is empty and the software tries to read data from the FIFO buffer, an underrun error is set. Before reading or writing data in the FIFO buffer, the software must read the FIFO buffer empty bit (fifo_empty) or FIFO buffer full bit (fifo_full) in the status register.
  • Data starvation by host timeout—This condition occurs when software does not service the FIFO buffer fast enough to keep up with the controller. Under this condition and when a read transfer is in process, the software must read data from the FIFO buffer, which creates space for further data reception. When a transmit operation is in process, the software must write data to fill the FIFO buffer so that the controller can write the data to the card.
  • CE‑ATA errors
  • CRC error on command—If a CRC error is detected for a command, the CE‑ATA card device does not send a response, and a response timeout is expected from the controller. The ATA layer is notified that an MMC transport layer error occurred.
  • Write operation—Any MMC transport layer error known to the card device causes an outstanding ATA command to be terminated. The ERR bits are set in the ATA status registers and the appropriate error code is sent to the Error Register (Error) on the ATA card device.

    If the device interrupt bit of the CE‑ATA card (the nIEN bit in the ATA control register) is set to 0, the CCS is sent to the host.

    If the device interrupt bit is set to 1, the card device completes the entire data unit count if the host controller does not abort the ongoing transfer.

    Note: During a multiple‑block data transfer, if a negative CRC status is received from the card device, the data path signals a data CRC error to the BIU by setting the dcrc bit in the rintsts register to 1. It then continues further data transmission until all the bytes are transmitted.
  • Read operation—If MMC transport layer errors are detected by the host controller, the host completes the ATA command with an error status. The host controller can issue a CCSD command followed by a STOP_TRANSMISSION (CMD12) command to abort the read transfer. The host can also transfer the entire data unit count bytes without aborting the data transfer.