Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

17.2. EMAC Block Diagram and System Integration

Figure 61. EMAC Block Diagram
Figure 62. EMAC System Integration

EMAC Overview

Each EMAC contains a dedicated DMA controller that masters Ethernet packets to and from the System Interconnect. The EMAC uses a descriptor ring protocol, where the descriptor contains an address to a buffer to fetch or store the packet data.

Each EMAC has an MDIO Management port to send commands to the external PHY. This port can be implemented using the I2C modules in the HPS or the EMAC's MDIO interface.

Each EMAC has an IEEE 1588 Timestamp interface with 10 ns resolution. The ARM® Cortex-A53 MPCore processor can use it to maintain synchronization between the time counters that are internal to the three MACs. The clock reference for the timestamp can be provided by the Clock Manager (emac_ptp_clk) or the FPGA fabric (f2h_emac_ptp_ref_clk). The clock reference is selected by the ptp_clk_sel bit in the emac_global register in the system manager.

Note: All three EMACs must use the same clock reference. In addition, EMAC0 can be configured to provide the timestamp for EMAC1, EMAC2, or both by setting the ptp_ref_sel bit in the emac* register in the System Manager.