Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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5.4.4. Translation Buffer Unit

The FPGA TBU caches page table walk results for FPGA-issued accesses to the FPGA-to-HPS bridge. Details of the FPGA TBU configuration are shown in the table below.

The remaining TBUs have the configuration shown in the "Peripheral Master TBU" column of the Translation Buffer Unit Configurations table below. The DMA and SDM each have their own dedicated peripheral master TBU. EMAC0 through EMAC2 share a peripheral master TBU. The USBs, NAND, SD/MMC, and Embedded Trace Router (ETR) share a peripheral master TBU.
Table 46.  Translation Buffer Unit Configurations
Parameter FPGA TBU Peripheral Master TBUs
AXI data bus width 512 bits 64 bits
Write buffer depth 16 entries 8 entries
TLB depth 128 entries 32 entries
TBU queue depth 8 entries 8 entries

The Cortex® -A53 MPCore™ has its own TBU configuration. Details on this TBU can be found in the Cortex® -A53 MPCore™ chapter.