Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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5.4.7. Stream ID

Each transaction is also classified by a 10-bit stream ID. The stream ID represents a set or stream of transactions from a particular master device. All transactions in a stream are subject to the same translation process. For example, the DMA controller may have multiple independent threads of execution that each form a different stream and can be subject to different translations. Alternatively, the peripheral masters on the system interconnect may share a single stream ID. Transactions from these devices can only be translated as a single entity. The TCU matches the stream ID against a set of stream match registers, SMMU_SMRx. The SSD determines the set of registers that are used. The secure software can partition the set into a non-secure set for use by SSD non-secure transactions and a secure set for use by SSD secure transactions. The stream matching process results in the following possible outcomes:

  • No matches: If no matches are found, you can select whether transactions bypass the SMMU.
  • Multiple match: If multiple SMMU_SMRn matches are found, the SMMU faults the transactions. The fault detection for these transactions is imprecise.
  • Single match: If only a single match is found, the corresponding SMMU_S2CRn for the SMMU_SMRn that matched is used to determine the required additional processing steps.

For each SMMU_SMRn, there is a corresponding SMMU_S2CRn that is used when only a single SMMU_SMRn matches. The SMMU_S2CRn.TYPE bit field determines one of the following results:

  • Fault All transactions generate a fault. A client device receives a bus abort if SMMU_sCR0.GFRE == 1, otherwise the transaction acts as read-as-zero/write-ignored (RAZ/WI).
  • Bypass transactions bypass the SMMU.
  • Translate transactions are mapped to a context bank for additional processing. The SMMU_S2CRn.CBNDX bit field specifies the context bank to be used by the SMMU.

The second stage boot loader configures the stream ID for the SDM-to-HPS TBU interface. The FPGA-to-HPS interface provides its stream ID. You can specify the FPGA-to-HPS stream ID value in Intel® Quartus® Prime Pro Edition.

You can configure the stream ID for each HPS peripheral master through registers in the System Manager. The table below lists the peripheral masters, the corresponding System Manager register used to configure the stream ID and the specific bitfields that represent the stream ID. During a master access the stream ID source is provided as a part of the AxUSER[12:3] signals.

Table 47.  HPS Master Stream ID
Master System Manager Register Register Bitfields Corresponding to stream ID[9:0]
EMAC0 emac0_ace

awsid[29:20]

arsid[17:8]

EMAC1 emac1_ace

awsid[29:20]

arsid[17:8]

EMAC2 emac2_ace

awsid[29:20]

arsid[17:8]

USB0 usb0_l3master hauser22_13[25:16]
USB1 usb1_l3master hauser22_13[25:16]
DMA dma_l3master

aruser[25:16]

awuser[9:0]

NAND nand_axuser

aruser[25:16]

awuser[9:0]

ETR etr_l3master

aruser[25:16]

awuser[9:0]