Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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15.5.2.3.4. Configure for Main+Spare Area Access

To configure the NAND flash controller to access the main+spare area:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ ADDR field to the target block.
  2. Write 0x43 to the Data register.