Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

ID 814028
Date 6/07/2024
Public
Document Table of Contents

5.5. Validating Pins

Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors.

Refer to the Migrating Assignments to Another Target Device section in the Quartus® Prime Pro Edition User Guide: Design Constraints to verify if the pin assignments are compatible to different density devices in the same device package.