Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

ID 814028
Date 6/07/2024
Public
Document Table of Contents

7. Signal Integrity Simulations

Many factors impact high-speed, serial interface signal integrity, for example, Insertion Loss (IL), Insertion Loss Deviation (ILD), Return Loss (RL), crosstalk, and mode conversion. To mitigate these factors, first determine the loss budget for your targeted protocol. Second, select PCB materials and a stack up design that allow you to stay under your loss budget. Then design your PCB with these materials, and run channel compliance analysis.

The High-Speed Serial Interface Signal Integrity Design Guidelines provide detailed information on channel loss, PCB materials and stack up, and general PCB Design Recommendations. This information is also provided by Tile (E-Tile, F-Tile, P-Tile, and R-Tile).