Visible to Intel only — GUID: wtv1708316415074
Ixiasoft
1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles
2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
2.5.3. Agilex™ 7 I-Series Devices with F-Tiles
2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
2.5.6. Agilex™ 7 M-Series Devices without HBM2e
Visible to Intel only — GUID: wtv1708316415074
Ixiasoft
7. Signal Integrity Simulations
Many factors impact high-speed, serial interface signal integrity, for example, Insertion Loss (IL), Insertion Loss Deviation (ILD), Return Loss (RL), crosstalk, and mode conversion. To mitigate these factors, first determine the loss budget for your targeted protocol. Second, select PCB materials and a stack up design that allow you to stay under your loss budget. Then design your PCB with these materials, and run channel compliance analysis.
The High-Speed Serial Interface Signal Integrity Design Guidelines provide detailed information on channel loss, PCB materials and stack up, and general PCB Design Recommendations. This information is also provided by Tile (E-Tile, F-Tile, P-Tile, and R-Tile).