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1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles
2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
2.5.3. Agilex™ 7 I-Series Devices with F-Tiles
2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
2.5.6. Agilex™ 7 M-Series Devices without HBM2e
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2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
Device | Attribute | Package | |
---|---|---|---|
Package Code | R24B | R25A | |
Pin Count | 2486 | 2581 | |
Package Size (mm) | 55 x 42.5 | 52.5 x 40.5 | |
Pitch (mm) | 1 | 0.92/0.94 | |
Type | Hex | Hex | |
Number E-Tile | E-Tile x1 | E-Tile x1 | |
Number P-Tile | P-Tile x1 | P-Tile x2 | |
AGF 012 | GPIO (LVDS) E-Tile: 28.9G NRZ (57.8G PAM4) P-Tile: 16G PCIe* |
768 (384) 16 (8) 16 |
— |
AGF 014 | GPIO (LVDS) E-Tile: 28.9G NRZ (57.8G PAM4) P-Tile: 16G PCIe* |
768 (384) 16 (8) 16 |
— |
AGF 019 | GPIO (LVDS) E-Tile: 28.9G NRZ (57.8G PAM4) P-Tile: 16G PCIe* |
— | 480 (240) 24 (12) 32 |
AGF 023 | GPIO (LVDS) E-Tile: 28.9G NRZ (57.8G PAM4) P-Tile: 16G PCIe* |
— | 480 (240) 24 (12) 32 |
AGF 022 | GPIO (LVDS) E-Tile: 28.9G NRZ (57.8G PAM4) P-Tile: 16G PCIe* |
— | 624 (312) 24 (12) 32 |
AGF 027 | GPIO (LVDS) E-Tile: 28.9G NRZ (57.8G PAM4) P-Tile: 16G PCIe* |
— | 624 (312) 24 (12) 32 |
1 Conditional migration between AGF 019/023 and AGF 022/027 in the R25A package.