Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

ID 814028
Date 6/07/2024
Public
Document Table of Contents

6.4.2.4. R-Tile Transceivers

R-Tile is a transceiver tile that supports PCIe* configurations up to Gen5 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer Packet (TLP) Bypass modes. Gen3, Gen4, and Gen5 configurations are natively supported. R-Tile also supports up to 16 SerDes channels through a PHY Interface for PCIe* (PIPE) v5.1.1 in SerDes Architecture mode. R-Tile also supports Compute Express Link* ( CXL* ) protocol for exceptional I/O performance in moving compute workloads between CPU and FPGA.

Note: CXL* information is currently classified as Intel Confidential – CNDA Required.