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Ixiasoft
1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles
2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
2.5.3. Agilex™ 7 I-Series Devices with F-Tiles
2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
2.5.6. Agilex™ 7 M-Series Devices without HBM2e
Visible to Intel only — GUID: htn1713531704143
Ixiasoft
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
Device | Attribute | Package | |
---|---|---|---|
Package Code | R47A | R47B | |
Pin Count | 4700 | 4700 | |
Size (mm) | 56 x 66 | 56 x 66 | |
Pitch (mm) | 0.92 | 0.92 | |
Type | Hex | Hex | |
Tiles and No. | F-Tile x3 R-Tile x1 HBM2e |
F-Tile x4 HBM2e |
|
AGM 032 | GPIO (LVDS) F-Tile: FGT 32G NRZ (58G PAM4) F-Tile: FHT 58G NRZ (116G PAM4) R-Tile: 32G PCIe* ( CXL* ) Lanes |
768 (384) 48 (36) 8 (8) 16 (16) |
768 (384) 64 (48) 8 (8) — |
AGM 039 | GPIO (LVDS) F-Tile: FGT 32G NRZ (58G PAM4) F-Tile: FHT 58G NRZ (116G PAM4) R-Tile: 32G PCIe* ( CXL* ) Lanes |
768 (384) 48 (36) 8 (8) 16 (16) |
768 (384) 64 (48) 8 (8) — |