Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

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ID 814028
Date 6/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Product Family Plan 3. Package Information 4. Thermal Design Considerations 5. Pin Connection Guidelines and Pinouts 6. Printed Circuit Board (PCB) Design 7. Signal Integrity Simulations 8. Validation 9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
1. Introduction x
1.1. Status Definitions 1.2. Notifications 1.3. Secure Asset Access—Developer Zone Premium (DZP)
2. Product Family Plan x
2.1. Product Table Information 2.2. Part Number Decoder 2.3. Series/Package/Tile Comparison Table 2.4. Migration within a Package 2.5. Series Package Options Versus Tiles—Support I/O Counts 2.6. Package Comparison Tables
2.5. Series Package Options Versus Tiles—Support I/O Counts x
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles 2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles 2.5.3. Agilex™ 7 I-Series Devices with F-Tiles 2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles 2.5.5. Agilex™ 7 M-Series Devices with HBM2e 2.5.6. Agilex™ 7 M-Series Devices without HBM2e
3. Package Information x
3.1. Ball Grid Array (BGA) Package
3.1. Ball Grid Array (BGA) Package x
3.1.1. Package Mechanical Drawings 3.1.2. Package Ball Coordinates 3.1.3. Package PCB Footprints 3.1.4. Land Pattern PCB Design Recommendations (MAS)
4. Thermal Design Considerations x
4.1. Power Estimation and Analysis Tools 4.2. Compact Thermal Models (CTM) 4.3. Heat Sink 4.4. Remote Temperature Sensing using Temperature Sensing Diodes (TSDs)
4.1. Power Estimation and Analysis Tools x
4.1.1. Intel® FPGA Power and Thermal Calculator (PTC) 4.1.2. Quartus® Prime Power Analyzer (QPA)
4.3. Heat Sink x
4.3.1. Heat Sink Rework
5. Pin Connection Guidelines and Pinouts x
5.1. Pin Connection Guidelines 5.2. Pinout Introduction 5.3. I/O Banks 5.4. Transceivers 5.5. Validating Pins
5.2. Pinout Introduction x
5.2.1. F-Series Pinouts 5.2.2. I-Series Pinouts 5.2.3. M-Series Pinouts 5.2.4. Hard Processor System (HPS) Pin Information 5.2.5. External Memory Interface (EMIF) Pin Information
5.3. I/O Banks x
5.3.1. Types of Banks 5.3.2. Bank Locations 5.3.3. Selecting Bank Usage
5.3.1. Types of Banks x
5.3.1.1. General-purpose I/O (GPIO) 5.3.1.2. Secure Device Manager (SDM) I/O 5.3.1.3. Hard Processor System (HPS) I/O
5.3.3. Selecting Bank Usage x
5.3.3.1. Agilex™ 7 M-Series FPGA I/O Placement
6. Printed Circuit Board (PCB) Design x
6.1. Schematic Symbols 6.2. Power Supply 6.3. External Memory 6.4. Transceivers 6.5. SoC FPGA Hard Processor Systems (HPS) 6.6. JTAG Interface 6.7. FPGA Configuration 6.8. Development Kit Examples 6.9. Schematic Review Worksheet 6.10. Step-by-Step Generic PCB Design Flow
6.4. Transceivers x
6.4.1. High-Speed Serial Interface Signal Integrity Design Guidelines 6.4.2. Tiles
6.4.2. Tiles x
6.4.2.1. F-Tile Transceivers 6.4.2.2. E-Tile Transceivers 6.4.2.3. P-Tile Transceivers 6.4.2.4. R-Tile Transceivers
6.10. Step-by-Step Generic PCB Design Flow x
6.10.1. Getting Ready 6.10.2. Schematic Design 6.10.3. Board Layout 6.10.4. Checks
7. Signal Integrity Simulations x
7.1. Intel Advanced Link Analyzer 7.2. Signal Integrity Analysis with Third-Party Tools 7.3. IBIS Models 7.4. Transceiver IBIS-AMI Models 7.5. Net Length Reports
8. Validation x
8.1. Validation and Debug Tools 8.2. Boundary-Scan Description Language (BSDL) Models
8.1. Validation and Debug Tools x
8.1.1. Transceiver Toolkit 8.1.2. EMIF Toolkit and Debug Tools 8.1.3. System Console 8.1.4. Signal Tap 8.1.5. Programmer’s Configuration Debugger Tool
8.2. Boundary-Scan Description Language (BSDL) Models x
8.2.1. Pre-Configuration BSDL Files 8.2.2. Post-Configuration BSDL Generator
1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

5.3.3. Selecting Bank Usage

Priority should be given to set up external memory interfaces as they also have additional bank restrictions. Within a GPIO bank there is a Top sub-bank and a Bottom sub-bank. Interconnects chain through the sub banks in a particular order (refer to the respective Agilex™ 7 General-Purpose User Guides for details) and prior to finalizing an EMIF pinout, run a sample design in the Quartus® Prime software to ensure the implementation is supported.

Also, while selecting the GPIO pins for other peripherals, you must know their location when placing peripheral devices (for example, buffers or level shifters if required) or connector locations to help create more optimal trace layouts.

Altera recommends setting up a simple I/O ring in the Quartus® Prime software to validate the placement of the I/O settings.


Section Content
Agilex 7 M-Series FPGA I/O Placement

Level Two Title