Visible to Intel only — GUID: urn1708316374515
Ixiasoft
1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles
2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
2.5.3. Agilex™ 7 I-Series Devices with F-Tiles
2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
2.5.6. Agilex™ 7 M-Series Devices without HBM2e
Visible to Intel only — GUID: urn1708316374515
Ixiasoft
6.10.4. Checks
In addition to standard tool checks along the way, additional post layout-premanufacture checks may include:
- Revisit power tree analysis now that all circuitry has been added to ensure selected regulators have the needed capacity. Also, check that all supplies have sufficient decoupling.
- Revisit Power Integrity checks for voltage droop and current density issues (power plane necks or insufficient via count)
- Review the HSSI (differential pair) traces for optimal layout and noise considerations.
- Run post-layout Signal Integrity simulations.
- Connector – review pinout and connector drawings to double check no flip or other connection problem has occurred. This is a common reported problem area.
- Revisit thermal simulations - with the board layout complete, a 3D model is now fully known for air flow/cooling simulations.