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1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles
2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
2.5.3. Agilex™ 7 I-Series Devices with F-Tiles
2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
2.5.6. Agilex™ 7 M-Series Devices without HBM2e
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Ixiasoft
6.10.1. Getting Ready
- Gather your system requirement documents that describe and specify the application’s function and mechanical requirements
- Gather up reference material. This can include Dev Kit examples, similar implementations, and any prior work to leverage.
- Gather PCB documentation and resources as needed (or when needed). The Pin Connection Guideline (PCG), Pinout, Configuration User Guide, Power Management User Guide, Schematic Symbol, PCB Footprint, and other needed assets.
- Confirm the targeted device/package for the application. This should include some preliminary FPGA IP builds for logic estimates and to ascertain clocking requirements etc. Vertical migration review is also key to allow the design to grow or shrink as your FPGA IP matures.
- Power Estimate and Thermal design. This will confirm application feasibility and the targeted heat sink designs.
Note: This is revisited once the FPGA IP build matures and must be confirmed once final.
- Pre-layout Power Integrity (PI) simulations for Power Distribution Network and Transient Noise Analysis
- Pre-layout Signal Integrity (SI) simulations for critical or new high-speed interfaces.