Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

ID 814028
Date 6/07/2024
Public
Document Table of Contents

5.3.1.2. Secure Device Manager (SDM) I/O

The SDM banks support 1.8 V singled-ended non-voltage referenced I/O standard signaling. These pins are used for configuration, power management, and device status signals.